1. Technical Field
The following embodiments generally relate to a digital circuit design and, more particularly, to a method and apparatus for injecting a fault and analyzing fault tolerance.
2. Description of the Related Art
As transistor sizes continue to shrink, transient faults have emerged as a major obstacle to the reliability of semiconductor components. As a result, fault tolerance mechanisms in semiconductors have attracted substantial attention in applications in which safety is essentially required. Applications in which safety is essentially required include applications in the automobile industry, the aviation industry, etc.
Fault tolerance analysis for digital circuits may be performed at several levels of abstraction depending on the circumstances. At a relatively low level, faults may be analyzed as being related to individual transistor elements, switches, and gates. At a relatively high level, faults may be analyzed at a Register Transfer Level (RTL) and a system level. In the following embodiments, a fault injection and fault analysis methodology will be described, and the digital circuit design at RTL level may be required as the target into which faults are to be injected and analyzed.
A Programming Language Interface (PLI) may be an Application Program Interface (API) for a Verilog Hardware Description Language (HDL). PLI may provide a means for invoking a C function from Verilog code. Further, PLI may be used for various objects. In the following embodiments, PLI may be used to extract information about a design to be utilized in the injection of faults and in the analysis of fault tolerance.
In spite of efforts to apply various fault tolerance mechanisms, no standard means for injecting faults and analyzing the effectiveness of an implemented fault tolerance mechanism has been proposed at the present time. In the following embodiments, a methodology and a required apparatus, which inject faults into the design of a Very Large Scale Integration (VLSI) processor and analyze the faults at development time, are described below.
In relation to fault injection and fault analysis, Korean Patent Application No. 2009-7007874 and U.S. Patent Application Publication Nos. 2011-0214014 and 2008-0263400 are disclosed.